• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a memory cell comprising a selection transistor (ST) having a control gate (GT) and a first conduction terminal (DDP) connected to a variable resistance element (VZ), the memory cell being formed in a wafer comprising a semiconductor substrate (SUB) covered with a first insulating layer (IL), the insulating layer being covered with an active layer (AL) of a semiconductor material, the gate being formed on the active layer and having a sidewall covered with a second insulating layer (SP), the variable resistance element (VR) comprising a first layer (VZ) covering a sidewall of the active layer in a trench (TR) formed through the active layer along the lateral side of the gate and reaching the first insulating layer, and a second layer (VZ) of a variable resistance material.
    公开号:FR3038133A1
    申请号:FR1555733
    申请日:2015-06-23
    公开日:2016-12-30
    发明作者:Philippe Boivin；Simon Jeannot
    申请人:STMicroelectronics Crolles 2 SAS；STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    [0001] The present invention relates to phase-change memories, and more generally to the memories in which each memory cell comprises a selection transistor and a variable impedance element that can have several different states that can be detected by an impedance measurement. Depending on whether the element can maintain its state with or without power supply, the memory is volatile or nonvolatile. FIGS. 1A, 1B schematically represent in section a semiconductor substrate SUB on which is formed a memory cell MC11 comprising a variable resistance element VZ. Fig. 1A is a longitudinal sectional view taken along the AN plane shown in Fig. 1B, and Fig. 1B is a cross-sectional view along the BB 'plane shown in Fig. 1A. The memory cell MC11 comprises a selection transistor comprising a gate GT, conduction regions (drain or source) DDP and SDP on either side of the gate GT, and a channel region under the gate GT between the regions of DDP conduction, SDP. The gate GT is made of a polycrystalline silicon layer formed on an insulating layer GO deposited on the substrate SUB. The DDP, SDP regions are formed by implanting dopants into the SUB substrate on either side of the GT gate. The memory cell MC11 is covered by a dielectric insulating material D1. The conduction region SDP is connected to a source line SL via a via passing through the insulating layer D1. The gate GT forms a word line WL extending parallel to the source line SL. The variable resistance element VZ is formed in the insulating layer D1 and is connected to the conduction region DDP via a via formed in the insulating layer D1. The variable resistance element VZ is connected to a bit line BL formed on the surface of the insulating layer D1 via a via BC formed in the insulating layer D1. The bit line BL is perpendicular to the word lines WL and source SL. The memory cell is isolated from adjacent memory cells (or other circuit elements formed on the SUB substrate) by shallow insulation trenches STI1 parallel to the gate GT, and insulation trenches little perpendicular 3038133 2 perpendicular STI2 at the GT grid. The isolation trenches STI1 may be replaced by transistor gates, such as the gate GT, biased so as to keep the associated transistor in the off state. The variable resistance element VZ is formed in a material capable of passing from an amorphous phase to a crystalline phase and vice versa, under the effect of heat. In its amorphous form, the element VZ has a high resistance, and in the crystalline form its resistance is weak. The element VZ is therefore associated in series with a heating element HT under the effect of the passage of a current. The amorphous form is obtained by applying a current peak to the HT heating element, while the crystalline form is obtained by slower cooling of the VZ element by gradually reducing the current flowing through the HT heating element. Some phase change materials may be controlled to present more than two phases having different resistances, which allows several bits to be stored in a single memory cell. FIG. 2 represents the electrical circuit of a part of a memory plane comprising memory cells such as the memory cell MC11 represented in FIGS. 1A, 1B. The memory plane comprises word lines WL, source lines SL parallel to the word lines WL and bit word lines perpendicular to the word lines WL and the source lines BL. Each memory cell MC11 comprises a selection transistor ST comprising a conduction terminal (source or drain) connected to a terminal of a variable resistance element VZ whose other terminal is connected to one of the bit lines BL. The other conduction terminal 25 of the selection transistor ST is connected to one of the source lines SL, and the gate terminal of the transistor ST is connected to one of the word lines WL. To reduce the area occupied by each memory cell, it has been proposed to make the memory cells in pairs, sharing a same SDP conduction region connected to a source line SL, as in Fig. 2. In this embodiment, the isolation trench ST1 on the left in FIG. 1A is replaced by a gate such as the gate GT to form the gate of the selection transistor of the other memory cell of the pair of memory cells.
    [0002] It is desirable to further reduce the occupied substrate area by a memory cell comprising a variable resistance element. Embodiments relate to a memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable resistance element, the memory cell being formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer of a semiconductor material, the gate being formed on the active layer and having a sidewall covered with a second insulating layer, the variable resistance element comprising a first layer covering a sidewall of the active layer in a trench formed through the active layer along the sidewall of the grid and reaching the first insulating layer, and a second layer of a variable resistance material. According to one embodiment, the first and second layers form the same layer. According to one embodiment, the first layer covers a lateral flank of a conductive trench.
    [0003] According to one embodiment, an upper portion of the first layer is in contact with a conductive layer extending in a plane parallel to the surface of the substrate. According to one embodiment, the first layer covers a lateral flank of an insulating trench formed under the conductive layer.
    [0004] According to one embodiment, the second layer extends in a plane parallel to the surface of the substrate and is in contact with an upper portion of the first layer which provides a heating element function for heating the second layer to changing the phase between a very weak amorphous phase and a very conductive crystalline phase. Embodiments may also relate to a memory comprising at least two memory cells as previously defined, the control gate of each memory cell being connected to a word line of the memory, the variable resistance element of each memory cell being connected to a bit line of the memory, the selection transistor 3038133 4 of each memory cell including a second conduction terminal connected to a source line of the memory. According to one embodiment, the variable resistance elements of the two memory cells are formed in the trench and are separated from each other by the conductive trench connected to the same bit line. According to one embodiment, the second conduction terminal of each memory cell is shared with another memory cell of the memory. Embodiments may also relate to a method of manufacturing an integrated circuit comprising a memory cell, the method comprising the steps of: forming a selection transistor on a semiconductor substrate covered with a first insulating layer, the insulating layer being coated with an active layer of a semiconductor material, the selection transistor comprising a control gate and first and second conduction terminals, covering with a second insulating layer a lateral flank of the control gate on the side of the first conduction terminal, making a first trench through the active layer in the first conduction terminal, reaching the first insulating layer, depositing a first layer in the first trench, covering a sidewall of the active layer in the trench, and deposit a second layer of variable resistance material. According to one embodiment, the first and second layers form the same layer. According to one embodiment, the method comprises steps of depositing on one lateral side of the first layer of a third insulating layer, and etching of a second trench in the first layer along the third insulating layer, until In one embodiment, the method comprises a step of filling the second trench with a conductive material to form a conductive trench. According to one embodiment, the method comprises steps of filling the second trench with an insulating material and depositing on the second trench a conductive material in contact with the first layer of a variable resistance material.
    [0005] According to one embodiment, the second layer extends in a plane parallel to the surface of the substrate and is in contact with an upper portion of the first layer which provides a heating element function to heat the second layer in order to change phase 5 between a very weak amorphous phase and a very conductive crystalline phase. Exemplary embodiments of the invention will be described in the following, without limitation in connection with the appended figures among which: FIGS. 1A, 1 B, described above, show schematically in transverse and longitudinal sections respectively, a semi substrate -conductor in which is formed a conventional memory cell comprising a variable resistance element, Figure 2 described above, schematically shows the electrical circuit of a portion of a memory plane comprising variable resistance element memory cells, such as 1A, 1B, 3A, 3B and 3C show schematically a semiconductor substrate in which memory cells are formed comprising a variable resistance element, according to one embodiment, respectively in cross section, in longitudinal section. and in plan view, FIGS. 4A to 4D are diagrammatic In cross-sectional view, a semiconductor substrate at different stages of manufacture of a memory cell such as that of FIG. 3A, according to one embodiment, FIGS. 5 and 6 show schematically in cross-section a semiconductor substrate in FIG. wherein memory cells comprising a variable resistance element are formed, according to other embodiments, FIG. 7 schematically represents the electrical circuit of a portion of a memory plane comprising variable resistance element memory cells, such as 3A, 5 or 6. FIGS. 3A, 3B, 3C show a semiconductor substrate SUB on which a memory cell MC1 is formed comprising a variable resistor element VZ, according to one embodiment. Figure 3A is a sectional view along the plane AN shown in Figure 3B, and Figure 3B is a sectional view along the plane BB 'shown in Figure 3A. The substrate SUB is silicon on insulator type SOI (Silicon on Insulator) and comprises an insulating layer IL formed on one side of the substrate SUB and an active layer AL in a semiconductor material, for example made of silicon, formed on the layer insulating IL. The SUB substrate may be FDSOI (Fully Depleted SOI) type. The memory cell MC1 comprises a selection transistor comprising a gate GT formed on the SUB substrate, and SDP and DDP conduction regions respectively formed on both sides of the gate GT. The gate GT is formed of a conductive material such as doped polycrystalline silicon, on an insulating layer GO, for example oxide SiO 2, deposited on the active layer AL. The GT grid forms a channel region between the DDP and SDP regions. The SDP and DDP regions are made by implanting dopants into the active layer AL. The SDP region thus forms a conduction region common to the selection transistors of the memory cell MC1 and an adjacent memory cell. A via connects the SDP region to a SL source line. The grid GT is covered with a dielectric layer SP forming spacer on the lateral flanks of the grid GT. The memory cell MC1 is covered by one or more layers DL, D1 of dielectric insulating material which may also be SiO2 oxide or a metal oxide. According to one embodiment, a trench is made between the spacers SP of the gate GT and an adjacent gate GT1, through the active layer AL in the region DDP, until reaching the insulating layer IL. A layer of variable resistance material is deposited and etched to form variable resistance elements VZ covering SP spacers, part of the bottom of the trench between spacers SP, and in particular lateral flanks of active layer AL. in the trench. Beforehand, PI barriers impervious to the diffusion of species present in the VZ layer to the active layer AL, are produced for example by siliciding of the silicon forming the active layer AL. The barriers PI make it possible to prevent the material forming the layer VZ from polluting the active layer AL forming the selection transistor. SP1 spacers are formed on the lateral flanks of the trench covered by variable resistance elements VZ. The trench is filled with a conductive material so as to form a conductive trench BC reaching the insulating layer IL between the variable resistance elements VZ, without coming into contact with the upper part of the VZ elements.
    [0006] In Figs. 3B and 3C, adjacent memory cells are isolated from each other by adjacent STI2 isolation trenches formed in the active layer AL and reaching the insulating layer IL. The conductive trench BC and the variable resistor elements VZ are cut into sections above the insulation trenches STI2, in order to isolate each memory cell from the adjacent memory cells located beyond the adjacent STI2 isolation trenches, and thus avoiding the formation of conductive filaments between two BL bit lines within the material forming the elements VZ. The variable resistance layer VZ may be made of a chalcogenide glass such as GST, an alloy of germanium, antimony and tellurium (Ge2Sb2Te5). By applying a sufficiently high current, this material heats up and can change phase between an amorphous phase and a crystalline phase depending on the cooling rate applied to the material. The latter does not need to be associated with a heating element.
    [0007] With these arrangements, the layer of variable resistance material forms a variable resistance element VZ, for both the memory cell MC1 and the adjacent memory cell MC2 having the gate GT1. Thus, the memory cell structure which has just been described makes it possible to offer a relatively large substrate area gain by virtue of the fact that the connection to the bit line BL of the variable resistance elements of the adjacent memory cells MC1, MC2 is made. , is shared by the two memory cells. With respect to the structure shown in Figs. 1A, 1B, the memory cell structure shown in Figs. 3A to 3C provides a substrate surface gain of about 29%, keeping the dimensions of the memory cell components. Figs. 4A to 4D show a portion of the SUB substrate on which a pair of memory cells are formed. FIG. 4A shows the substrate after the realization of the grids GT, GT1 and spacers SP formed on the lateral flanks of the grids GT, GT1. During a manufacturing step 35 illustrated in FIG. 4A, a trench TR is formed in the active layer 3038133 8 AL between the spacers SP formed along the grids GT, GT1, the trench TR being made so as to reach the insulating layer IL . At the following manufacturing steps, illustrated in FIG. 4B, insulation of the flanks of the trench TR in the active layer AL is carried out so as to form IP insulating elements in the active layer AL in the vicinity of the lateral flanks of the trench. trench TR. This operation is performed for example by nitriding the silicon forming the active layer AL. Substrate SUB is then covered with a DL dielectric layer, including trenches TR. The DL layer is for example 10 made of a metal oxide. At the following manufacturing steps, illustrated in FIG. 4C, the layer DL is etched so as to form a trench TR1 corresponding to the trench TR, while leaving a portion of the layer DL on the grids GT, GT1. The surface of the substrate and trenches TR1 are then covered with a substantially uniform thickness layer VL of the material for forming the variable resistance elements. SP1 spacers are formed on the sides of trench TR1 covered with the VL layer, for example in GST. At the following manufacturing steps, illustrated in FIG. 4D, the layer VL not covered by the spacers SP1 is etched until reaching the insulating layer at the bottom of the trench TR1 between the spacers SP1, so as to individualize the elements. variable resistance VZ. The formation of spacers SP, SP1, ensures a centering of the uncovered region at the bottom of trench TR1, between grids GT, GT1. Trench TR1 is then filled with conductive material to form a conductive trench BC. For this purpose, the walls and the bottom of trench TR1 may for example be covered with a conductive layer of substantially uniform thickness, for example titanium or titanium nitride. Trench TR1 can then be filled with a metal such as tungsten or copper. In subsequent steps, vias V1 (see Fig. 3A) for connection of the SDP regions may be formed in the DL layer, and SL source lines connected to the vias V1 may be formed on the DL layer. The entire substrate (DL layer and SL source lines) is covered with the dielectric layer D1 (Figure 3C) which is then etched to form a connection via the conductive trench BC to a bit line BL. The layers DL, D1 can be made in PMD (Polysilicon Metal Dielectric). FIG. 5 shows a semiconductor substrate SUB on which memory cells MC3, MC4, each comprising a variable resistance element VZ, according to another embodiment, are formed. The memory cells MC3, MC4 differ from the memory cells MC1, MC2 in that the trench TR1 between the spacers SP1 is filled by a dielectric material D2, and a conductive layer CL is formed above the trench TR1 on the material D2, in order to be in electrical contact with an upper region of the elements VZ. The layer CL can be connected to a bit line BL via a via V2. Note that Via V2 can connect the VZ element directly to the BL bit line. The layer D2 can be made in PMD. FIG. 6 shows a semiconductor substrate SUB on which memory cells MC5, MC6 are formed, sharing the same variable resistor element VZ ', according to another embodiment. The memory cells MC5, MC6 differ from the memory cells MC3, MC4 in that the variable resistance elements VZ of the memory cells MC3, MC4 are replaced by HT elements of the same shape and therefore can be produced in the same way, simply replacing the VL layer with a layer of resistive heat-dissipating material at the voltages that may be applied between the source line contacts SL and the bit line BL of one of the memory cells. The conductive layer CL of the memory cells MC3, MC4 is also replaced by the variable resistance element VZ 'formed in a layer of variable resistance material. The element VZ 'is made to be in electrical contact with an upper part of each of the heating elements HT of the memory cells MC5, MC6. In this way, when one of the memory cells MC5, MC6 is to be programmed or erased, a current flows in the element HT of the memory cell and in the element VZ ', and heats the heating element HT. As a result, the element VZ 'is locally heated by the element HT in a region in the vicinity of the zone of contact with the heating element HT. As a result, this region can change state between the crystalline phase and the amorphous phase. The regions of the variable resistance layer of the element VZ 'in the vicinity of the zone of contact with one of the heaters HT of the memory cells MC5, MC6 are sufficiently distant from each other that a phase change (amorphous / crystalline) of one of these regions does not cause a phase change of the other of these regions.
    [0008] Note that in the embodiment illustrated in FIG. 6, it is not necessary to form the IP insulating elements since the GST material is not in contact with a semiconductor material such as that of the active layer. AL. In the embodiments of Figures 5 and 6, SP1 spacers 10 may be omitted since it is not necessary to center elements relative to each other. FIG. 7 diagrammatically represents the electric circuit of a part of a memory plane MA comprising memory cells MC with variable resistance element VR, such as the memory cell MC1, MC3 or MC5. The memory plane MA comprises bit lines BL, word lines WL perpendicular to the bit lines BL and source lines SL perpendicular to the bit lines BL. Each memory cell MC comprises a selection transistor ST, and a variable resistance element VR such that the element VZ shown in FIG. 3A or 5, or the combination of a heating element HT with the layer VZ ', represented on FIG. Figure 6. The transistor ST has a conduction terminal (source or drain) connected to a terminal of the variable resistance element VR whose other terminal is connected to one of the bit lines BL. The other conduction terminal (drain or source) of the selection transistor ST is connected to one of the source lines SL. The transistor ST has a gate terminal connected to one of the word lines WL. The resistance of the VR element can be changed between a highly resistant state when the material forming the VR element is placed in an amorphous phase and a weakly resistant state when the material forming the VR element is placed in a crystalline phase.
    [0009] With respect to the memory array of FIG. 2, a large gain of substrate surface is obtained because each memory cell of the memory plane MA shares a connection point with a bit line BL with another memory cell of the memory plane, in addition to sharing a connection point to a source line SL of another memory cell.
    [0010] It should be noted that the DDP, SDP conduction regions of the selection transistor ST can form indifferently a drain terminal and a source terminal of the transistor, and that the functions of the bit lines BL and source SL can be interchanged. .
    [0011] The various embodiments of memory cells presented above can be carried out on a FDSOI (Fully Depleted SOI) type substrate, with IL active and insulating layers IL respectively having thicknesses of the order of 7 nm and 25 nm. The substrate employed can also be of PDSOI type (Partially Depleted SOI), with AL active and insulating layers IL respectively having thicknesses of the order of 25 nm and 100 nm. It will be apparent to those skilled in the art that the present invention is capable of various alternative embodiments and various applications. In particular, the invention is not limited to a memory, but also covers a single memory cell formed in an SOI type substrate. In this case in particular, it is not necessary to provide self-centering of the contact BC in the variable resistance material, since only one variable resistance element is to be produced. It should also be noted that the memory cell may be made on a conventional semiconductor substrate on which an insulating layer (IL) has been deposited, the semiconductor layer AL being formed on the insulating layer, for example by epitaxy.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. Memory cell comprising a selection transistor (ST) having a control gate (GT) and a first conduction terminal (DDP) connected to a variable resistance element (VZ), characterized in that it is formed in a wafer comprising a semiconductor substrate (SUB) covered with a first insulating layer (IL), the insulating layer being covered with an active layer (AL) in a semiconductor material, the gate (GT) being formed on the active layer and having a sidewall covered with a second insulating layer (SP), the variable resistance element (VR) comprising a first layer (VZ, HT) covering a sidewall of the active layer in a trench (TR) formed at through the active layer along the lateral side of the gate and reaching the first insulating layer, and a second layer (VZ, VZ ') of a variable resistance material.
    [0002]
    2. The memory cell of claim 1, wherein the first and second layers form a same layer (VZ).
    [0003]
    3. The memory cell of claim 2, wherein the first layer (VZ) covers a lateral flank of a conductive trench (BC).
    [0004]
    The memory cell of claim 2, wherein an upper portion of the first layer (VZ) is in contact with a conductive layer (CL) extending in a plane parallel to the surface of the substrate (SUB).
    [0005]
    5. The memory cell of claim 4, wherein the first layer (VZ) covers a lateral flank of an insulating trench (D2) formed under the conductive layer (CL). 30
    [0006]
    The memory cell of claim 1, wherein the second layer (VZ ') extends in a plane parallel to the surface of the substrate (SUB) and is in contact with an upper portion of the first layer (HT) which provides a heating element function for heating the second layer 3038133 13 to change its phase between a very weak amorphous phase and a highly conductive crystalline phase.
    [0007]
    7. Memory comprising at least two memory cells (MC1, MC2) according to one of claims 1 to 6, the control gate (GT) of each memory cell being connected to a word line (WL) of the memory, the variable resistance element (VZ) of each memory cell being connected to a bit line (BL) of the memory, the selection transistor (ST) of each memory cell comprising a second conduction terminal (SDP) connected to a source line (SL) of the memory.
    [0008]
    8. Device according to claim 7, wherein the variable resistance elements (VZ) of the two memory cells (MC1, MC2) are formed in the trench (TR) and are separated from each other by the conductive trench. (BC) connected to the same bit line (BL).
    [0009]
    9. Memory according to one of claims 7 to 8, wherein the second conduction terminal (SDP) of each memory cell (MC1, MC2) is shared with another memory cell memory. 20
    [0010]
    10. A method of manufacturing an integrated circuit comprising a memory cell (MC1, MC2), the method comprising the steps of: forming a selection transistor (ST) on a semiconductor substrate (SUB) covered by a first insulating layer (IL), the insulating layer being covered with an active layer (AL) of a semiconductor material, the selection transistor comprising a control gate (GT) and first and second conduction terminals (DDP, SDP), cover with a second insulating layer (SP) a lateral flank of the control gate on the side of the first conduction terminal (DDP), make a first trench (TR) through the active layer in the first conduction terminal, reaching the first insulating layer, depositing a first layer (VZ, HT) in the first trench, covering a lateral flank of the active layer in the trench, and depositing a second layer (VZ, VZ ') in a material to variable resistance.
    [0011]
    11. The method of claim 10, wherein the first and second layers form a same layer (VZ).
    [0012]
    12. The method of claim 11, comprising steps of depositing on a lateral flank of the first layer (VZ) of a third insulating layer (SP1), and of etching a second trench (TRI) in the first layer. along the third insulating layer, until reaching the first insulating layer,
    [0013]
    The method of claim 12 including a step of filling the second trench (TR1) with a conductive material to form a conductive trench (BC).
    [0014]
    The method of claim 12, comprising steps of filling the second trench (TR1) with an insulating material and depositing on the second trench (TR1) a conductive material in contact with the first layer of a material variable resistance (VZ).
    [0015]
    The method of claim 10, wherein the second layer (VZ ') extends in a plane parallel to the surface of the substrate (SUB) and is in contact with an upper portion of the first layer (HT) which provides a heating element function for heating the second layer in order to change its phase between a very weak amorphous phase and a highly conductive crystalline phase.
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1555733A|FR3038133B1|2015-06-23|2015-06-23|PHASE CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE|FR1555733A| FR3038133B1|2015-06-23|2015-06-23|PHASE CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE|
    US15/098,025| US9735353B2|2015-06-23|2016-04-13|Phase-change memory cell having a compact structure|
    US15/654,405| US20170317275A1|2015-06-23|2017-07-19|Phase-change memory cell having a compact structure|
    US16/457,855| US11031550B2|2015-06-23|2019-06-28|Phase-change memory cell having a compact structure|
    US17/328,917| US20210280779A1|2015-06-23|2021-05-24|Phase-change memory cell having a compact structure|
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